The dissemination of portable information devices in recent years has been spurring the needs for memory devices which are smaller and lighter and allow more saving of electric power and greater addition to capacity. As a large-capacity storage device promising to supersede the hard disk drive (HDD) which necessitates such a mechanical part as a motor, the solid state drive (SSD) using a NAND flash memory which is small, light, and capable of withstanding an external shock has been attracting attention. Though the NAND flash memory had a high unit cost in capacity as compared with the HDD magnetic disk, it has been enabled to penetrate the market rapidly by increasing the degree of integration of a memory array thereby lowering the unit cost in capacity.
To be specific, the NAND flash memory is formed of a memory array possessing a characteristic circuit configuration called a NAND type. The NAND flash memory has been developed progressively as a large-capacity memory because the degree of integration thereof can be augmented by compacting to the fullest possible extent the design layout of this memory array by the technology generation. The following two methods have been mainly adopted for the purpose of decreasing the unit cost in capacity by heightening the degree of integration of the memory array.
1) The first method consists in forming a memory device in a fine structure that allows the numbers of chips produced from one wafer to be increased.
2) In consideration of the fact that the storage in one memory cell is ordinarily made in one bit, namely that the judgment of the threshold voltage is made in the binary unit, the second method consists in decreasing the cost per bit by increasing the setting of the threshold value to the ternary unit or more.
The conventional memory cell, however, has about 10,000 rewritable cycles which are not a very large numbers, because this memory cell has been either a transistor possessing a floating gate capable of accumulating electric charge or a transistor possessing an insulating membrane capable of trapping electric charge.
It is said that when the fineness of structure is further pursued for the purpose of augmenting the degree of integration, the numbers of rewritable cycles will further decrease and the reliability of data will incur anxiety. Further since the conventional memory cell has been either a transistor possessing a floating gate capable of accumulating electric charge or a transistor possessing an insulating membrane capable of trapping electric charge, the voltage required for writing in the memory cell is about 20 V which is a large value. Thus, the conventional memory cell has entailed the problem that the electric current to be consumed is liable to be large because the low voltage supplied from the outside of the chip must be used after it has been heightened to about 20 V by the boosting circuit contained therein.
Then, when the fineness of structure of the conventional memory cell is further pursued, this fineness attained by the technique of production available after the so-called 30-nm generation is said to reach the limit owing to such problems as the leakage current between the floating gates of the adjacent memory cells and the capacity coupling noise. The formation of the NAND flash memory while using the conventional memory cell in the multivalued structure entails the problem that the writing and reading speeds will be decreased by the multistage decision of the threshold. Further, the conventional memory cell has entailed the problem that the increase of dispersion of the threshold voltages results in decreasing the difference between varied thresholds, rendering the discrimination of varied states of storage difficult, and further decreasing the numbers of writable cycles as a result.
As one method for solving the problems described above, the NAND-type random access memory of the binary memory and decision method using a ferroelectric gate transistor (FeFET) for a memory cell has been proposed (refer to Patent Document 1, for example). Since the ferroelectric materials generally have high prices and manifest widely varied solid state properties as compared with silicon, silicon oxide, and materials almost equivalent to silicon, the process for manufacturing the FeFET is liable to be complicated. When this state of affairs is taken into consideration, the introduction of the ferroelectric material into the NAND flash memory incurs another problem that the memory itself, while still resorting to the binary memory and decision method, is not feasible because the increase of cost per bit inevitably offsets the advantage of enhanced performance.
Meanwhile, the conventional technique concerning the device structure or storage method which is intended to subject the FeFET unit to multivalued storage has entailed the following problems.
As regards the device structure for subjecting the FeFET unit to the multivalued storage, for example, the semiconductor storage device which is vested with a multivalued nonvolatile storage by manufacturing a configuration which has memory function parts of a ferroelectric material attached to the side walls of a gate electrode has been proposed (refer to Patent Document 2, for example). In the case of the semiconductor storage device of this configuration, however, since the planar dimension of the memory function parts must be enlarged to the extent of enabling the multivalued nonvolatile storage to be discerned, there ensues the problem that, in the configuration of the transistor, particularly the layout area of the region of diffusion is enlarged and the degree of integration is lowered. As a method of storage for implementing the multivalued storage, the method which effects multivalued nonvolatile storage by a procedure that comprises manufacturing a configuration intentionally causing the gate electrode and the source area or drain area of FeFET to be piled up in the longitudinal direction and consequently inducing varied polarizations in the three parts composed of two ferroelectric bodies lying directly above two regions of diffusion and a ferroelectric material intervening therebetween has been proposed (refer to Patent Document 3, for example). In the case of this method, however, the fact that the three parts above-mentioned must be made to possess a mutually equal planar dimension gives rise to the problem that the layout area particularly of the gate area of the FeFET is enlarged and the degree of integration is lowered.
As the conventional storage device adapted for inducing multivalued storage in the FeFET unit, the ferroelectric memory that is enabled to acquire multivalued nonvolatile storage by interposing three voltages of varied magnitudes between the gate electrode and the substrate has been proposed (refer to Patent Document 4, for example). In the case of the memory so designed, since it is required to prepare many voltage sources, it incurs the problem that the numbers of circuits necessary for preparing a plurality of voltage sources inevitably increases.    Patent document 1: Japanese Unexamined Patent Publication No. 2001-24163    Patent document 2: Japanese Unexamined Patent Publication No. 2004-349310    Patent document 3: Japanese Unexamined Patent Publication No. 2006-108648    Patent document 4: Japanese Unexamined Patent Publication No. 8-124378/1996